The chip layout problem: A placement procedure for lsi
DAC '77 Proceedings of the 14th Design Automation Conference
The chip layout problem: An automatic wiring procedure
DAC '77 Proceedings of the 14th Design Automation Conference
A discrete heuristics approach to predictive evaluation of semi-custom IC layouts
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Electrical design of signal lines for multilayer printed circuit boards
IBM Journal of Research and Development
On-chip wiring for VLSI: status and directions
IBM Journal of Research and Development
Optimal folding of standard and custom cells
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A method of measuring nets routability for MCM's general area routing problems
ISPD '99 Proceedings of the 1999 international symposium on Physical design
PLEST: a program for area estimation of VLSI integrated circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Cost based tradeoff analysis of standard cell designs
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
A topology for semicustom array-structured LSI devices, and their automatic customisation
DAC '83 Proceedings of the 20th Design Automation Conference
IBM 3081 system overview and technology
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
An interactive system for VLSI chip physical design
IBM Journal of Research and Development
Stand-alone wiring program for Josephson logic
IBM Journal of Research and Development
A high-density bipolar logic masterslice for small systems
IBM Journal of Research and Development
Wire length distribution for placements of computer logic
IBM Journal of Research and Development
Semiconductor logic technology in IBM
IBM Journal of Research and Development
IBM Journal of Research and Development
System development and technology aspects of the IBM 3081 processor complex
IBM Journal of Research and Development
Influence on LSI package wireability of via availability and wiring track accessibility
IBM Journal of Research and Development
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
A stochastic model is developed for estimating wiring space requirements for one-dimensional layouts. This model uses as input the number of devices in the complex to be wired, the average length of a connection, and the average number of connections per device, to compute the probability of successfully wiring the devices as a function of the number of tracks provided. A heuristic approach is used to extend this model to the two-dimensional case, and tested against experimen-tal studies. Satisfactory agreement is found between a priori calculations of track requirements for the two-dimensional case against global wiring solutions for artificially generated problems, and for some layouts of actual logic complexes.