The effect of register-transfer design tradeoffs on chip area and performance
DAC '83 Proceedings of the 20th Design Automation Conference
Prediction of wiring space requirements for LSI
DAC '77 Proceedings of the 14th Design Automation Conference
CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Predicting area-time tradeoffs for pipelined design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A discrete heuristics approach to predictive evaluation of semi-custom IC layouts
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A new placement level wirability estimate with measurements
ACM SIGDA Newsletter
A module area estimator for VLSI layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A new area and shape function estimation technique for VLSI layouts
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Module selection for pipelined synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Area and power consumption estimations at system level with SystemQ 2.0
Proceedings of the 2nd International Conference on Simulation Tools and Techniques
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This paper describes PLEST, a program for estimating the area of standard cell layouts as part of the more general ARREST area estimator embedded in the ADAM system. PLEST is based on a probabilistic model for placement of logic. Given various design parameters, PLEST generates a range of estimates for the possible shapes of the block layout. The program was applied to a set of six layouts. The estimated chip area is, for all six chips, within 10% of the measured area. Further research will be aimed at estimating layout area consumption starting from the register-transfer level design description.