The C programming language
Benchmarks for cell-based layout systems
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A new approach to the rectilinear Steiner tree problem
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A module area estimator for VLSI layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A new area and shape function estimation technique for VLSI layouts
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Optimal aspect ratios of building blocks in VLSI
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
LocusRoute: a parallel global router for standard cells
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A data structure for circuit net lists
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
PLEST: a program for area estimation of VLSI integrated circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Graph Algorithms
Computer Algorithms: Introduction to Design and Analysis
Computer Algorithms: Introduction to Design and Analysis
A new statistical model for gate array routing
DAC '83 Proceedings of the 20th Design Automation Conference
Efficient placement and routing techniques for master slice LSI
DAC '80 Proceedings of the 17th Design Automation Conference
Using controlled experiments in layout
ACM SIGDA Newsletter
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An extension of the wirability estimate concept to master slice placement is presented. This estimate is usable on individual circuits, produces detailed wire requirement maps, but requires target designs to be at least partially placed. The main innovation is the discovery of an outer rectangle estimate that separates basic wire requirements from routing details. The estimate averages wires within one chip but is inapplicable to chip type wire space modeling. Steiner tree net decomposition, the half perimeter wire length estimate, and potential wire requirement reduction from a third metal layer are evaluated.