A module area estimator for VLSI layout

Authors:
Xinghao Chen;Michael L. Bushnell
Affiliations:
CAIP Research Center, Department of Electrical and Computer Engineering, Rutgers University P.O. Box 909, Piscataway, New Jersey;CAIP Research Center, Department of Electrical and Computer Engineering, Rutgers University P.O. Box 909, Piscataway, New Jersey
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

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Abstract

An efficient Module Area Estimator for VLSI chip layout has been developed to reduce the number of design iterations required to develop a chip floor plan. Module area is estimated for Standard-Cell and Full-Custom layout methodologies. We discuss the structure of the estimator and its algorithms. The layout area estimates are very close to those of manually laid out modules.