Average interconnection length and interconnection distribution based on rent's rule
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An intelligent component database for behavioral synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A module area estimator for VLSI layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A new area and shape function estimation technique for VLSI layouts
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
EURO-DAC '92 Proceedings of the conference on European design automation
On the intrinsic rent parameter and spectra-based partitioning methodologies
EURO-DAC '92 Proceedings of the conference on European design automation
A layout estimation algorithm for RTL datapaths
DAC '93 Proceedings of the 30th international Design Automation Conference
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
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We address the problem of area prediction of VLSI layouts. We present an approach based on two models, analytical and constructive. A circuit design is recursively partitioned down to a level specified by the user, thus generating a slicing tree. An analytical model is then used to predict the shape functions of the leaf subcircuits. By traversing the tree bottom up the shape function of the entire layout design can then be constructively predicted. This approach permits the user to trade off the accuracy of the prediction versus the runtime of the predictor. Such a scheme is quite useful for high-level synthesis and system level partitioning. The experimental validation results are quite good, indicating an average error of the order of 5% in predicting shape functions for Standard Cell benchmark designs with sizes ranging from 125 to 12,000 cells.