3D scheduling: high-level synthesis with floorplanning
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A module area estimator for VLSI layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A new area and shape function estimation technique for VLSI layouts
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
LAST: a Layout Area and Shape function esTimator for high level applications
EURO-DAC '91 Proceedings of the conference on European design automation
An approach for redesigning in data path synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Deriving efficient area and delay estimates by modeling layout tools
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
COMET: a hardware-software codesign methodology
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
False path exclusion in delay analysis of RTL-based datapath-controller designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Modeling layout tools to derive forward estimates of area and delay at the RTL level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
False path exclusion in delay analysis of RTL structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Lower bound estimation of hardware resources for scheduling in high-level synthesis
Journal of Computer Science and Technology
Accurate area and delay estimation from RTL descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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