Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A layout estimation algorithm for RTL datapaths
DAC '93 Proceedings of the 30th international Design Automation Conference
Estimating architectural resources and performance for high-level synthesis applications
DAC '93 Proceedings of the 30th international Design Automation Conference
Comprehensive lower bound estimation from behavioral descriptions
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Loop pipelining for scheduling multi-dimensional systems via rotation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Computing lower bounds on functional units before scheduling
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Timing estimation for behavioral descriptions
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Execution interval analysis under resource constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Estimation of lower bounds in scheduling algorithms for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An effective methodology for functional pipelining
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
On lower bounds for scheduling problems in high-level synthesis
Proceedings of the 37th Annual Design Automation Conference
Lower bound estimation for low power high-level synthesis
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Estimating Lower-Bound Performance of Schedules Using a Relaxation Technique
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Estimating lower hardware bounds in high-level synthesis
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
A unified lower bound estimation technique for high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Functional area lower bound and upper bound on multicomponent selection for interval scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Lower-bound performance estimation for the high-level synthesis scheduling problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In high-level synthesis of VLSI circuits, good lower bound prediction can efficiently narrow down the large space of possible designs. Previous approaches predict the lower bound by relaxing or even ignoring the precedence constraints of the data flow graph (DFG), and result in inaccuracy of the lower bound. The loop folding and conditional branch were also not considered. In this paper, a new stepwise refinement algorithm is proposed, which takes consideration of precedence constraints of the DFG to estimate the lower bound of hardware resources under time constraints. Processing techniques to handle multi-cycle. chaining, pipelining, as well as loop folding and mutual exclusion among conditional branches are also incorporated in the algorithm. Experimental results show that the algorithm can produce a very tight and close to optimal lower bound in reasonable computation time.