Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Optimal allocation and binding in high-level synthesis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
InSyn: integrated scheduling for DSP applications
DAC '93 Proceedings of the 30th international Design Automation Conference
Computing lower bounds on functional units before scheduling
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
SMASH: a program for scheduling memory-intensive application-specific hardware
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Execution interval analysis under resource constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Estimating Lower-Bound Performance of Schedules Using a Relaxation Technique
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
An exact methodology for scheduling in a 3D design space
ISSS '95 Proceedings of the 8th international symposium on System synthesis
A comprehensive estimation technique for high-level synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Lower bounds on test resources for scheduled data flow graphs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Estimation of lower bounds in scheduling algorithms for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Estimation of BIST Resources During High-Level Synthesis
Journal of Electronic Testing: Theory and Applications
On lower bounds for scheduling problems in high-level synthesis
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Lower bound estimation of hardware resources for scheduling in high-level synthesis
Journal of Computer Science and Technology
High-Level Synthesis of Recoverable Microarchitectures
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Storage requirement estimation for optimized design of data intensive applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compile-time area estimation for LUT-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast memory footprint estimation based on maximal dependency vector calculation
Proceedings of the conference on Design, automation and test in Europe
Computation of storage requirements for multi-dimensional signal processing applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integrated Computer-Aided Engineering
Journal of Signal Processing Systems
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications
Journal of Signal Processing Systems
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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In this paper, we present a comprehensive technique for lower bound estimation (LBE) of resources from behavioral descriptions. Previous work has focused on LBE techniques that use very simple cost models which primarily focus on the functional unit resources. Our cost model accounts for storage resources in addition to functional resources. Our timing model uses a finer granularity that permits the modeling of functional unit, register and interconnect delays. We tested our LBE technique for both functional unit and storage requirements on several high-level synthesis benchmarks and observed near-optimal results.