Compile-time area estimation for LUT-based FPGAs

Authors:
Dhananjay Kulkarni;Walid A. Najjar;Robert Rinker;Fadi J. Kurdahi
Affiliations:
University of California, Riverside, Riverside, CA;University of California, Riverside, Riverside, CA;University of Idaho, Moscow, ID;University of California, Irvine, Irvine, CA
Venue:
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Year:
2006

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Abstract

The Cameron Project has developed a system for compiling codes written in a high-level language called SA-C, to FPGA-based reconfigurable computing systems. In order to exploit the parallelism available on the FPGAs, the SA-C compiler performs a large number of optimizations such as full loop unrolling, loop fusion and strip-mining. However, since the area on an FPGA is limited, the compiler needs to know the effect of compiler optimizations on the FPGA area; this information is typically not available until after the synthesis and place and route stage, which can take hours. In this article, we present a compile-time area estimation technique to guide SA-C compiler optimizations. We demonstrate our technique for a variety of benchmarks written in SA-C. Experimental results show that our technique predicts the area required for a design to within 2.5% of actual for small image processing operators and to within 5.0% for larger benchmarks. The estimation time is in the order of milliseconds, compared with minutes for the synthesis tool.