An automated process for compiling dataflow graphs into reconfigurable hardware

Authors:
Robert Rinker;Margaret Carter;Amitkumar Patel;Monica Chawathe;Charlie Ross;Jeffrey Hammes;Walid A. Najjar;Wim Böhm
Affiliations:
Colorado State Univ., Ft. Collins, CO;Colorado State Univ., Ft. Collins, CO;Colorado State Univ., Ft. Collins, CO;Colorado State Univ., Ft. Collins, CO;Colorado State Univ., Ft. Collins, CO;Colorado State Univ., Ft. Collins, CO;Colorado State Univ., Ft. Collins, CO;-
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Year:
2001

Citing 0
Cited 14

A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture

CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
A compiler approach to fast hardware design space exploration in FPGA-based systems

PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
Processor Array Synthesis from Shift-Variant Deep Nested Do Loops

The Journal of Supercomputing
A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Data communication estimation and reduction for reconfigurable systems

Proceedings of the 40th annual Design Automation Conference
High-Level Language Abstraction for Reconfigurable Computing

Computer
Spatial computation

ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Compile-time area estimation for LUT-based FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)
An overview of reconfigurable hardware in embedded systems

EURASIP Journal on Embedded Systems
Mapping streaming architectures on reconfigurable platforms

ACM SIGARCH Computer Architecture News - Special issue on the 2006 reconfigurable and adaptive architecture workshop
Intelligent Decoupled SAC-SVD Method in Color Space Transformation of Computer Vision

IEA/AIE '09 Proceedings of the 22nd International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems: Next-Generation Applied Intelligence
Modern development methods and tools for embedded reconfigurable systems: A survey

Integration, the VLSI Journal
Compiling for reconfigurable computing: A survey

ACM Computing Surveys (CSUR)
Nominal decomposition of colour space transformation for the computer system for the reconfigurable computing and SA-C programming

International Journal of Computer Applications in Technology

Quantified Score

Hi-index	0.00

Visualization

Abstract

We describe a system, developed as part of the Cameron project, which compiles programs written in a single-assignment subset of C called SA-C into dataflow graphs and then into VHDL. The primary application domain is image processing. The system consists of an optimizing compiler which produces dataflow graphs and a dataflow graph to VHDL translator. The method used for the translation is described here, along with some results on an application. The objective is not to produce yet another design entry tool, but rather to shift the programming paradigm from HDLs to an algorithmic level, thereby extending the realm of hardware design to the application programmer.