Processor Array Synthesis from Shift-Variant Deep Nested Do Loops

Authors:
Surin Kittitornkun;Yu Hen Hu
Affiliations:
Department of Computer Engineering King Mongkut's Institute of Technology Ladkrabana, Bangkok, 10520 Thailand kksurin@kmitl.ac.th;Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI 53706 hu@engr.wisc.edu
Venue:
The Journal of Supercomputing
Year:
2003

Citing 13
Cited 0

VLSI array processors

VLSI array processors
Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms

IEEE Transactions on Computers
A Systolic Design Methodology with Application toFull-Search Block-Matching Architectures

Journal of VLSI Signal Processing Systems
The Organization of Computations for Uniform Recurrence Equations

Journal of the ACM (JACM)
MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications

IEEE Transactions on Computers
DG2VHDL: A Tool to Facilitate the High Level Synthesisof Parallel Processing Array Architectures

Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
An automated process for compiling dataflow graphs into reconfigurable hardware

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
High Performance Compilers for Parallel Computing

High Performance Compilers for Parallel Computing
Application of Reconfigurable Computing to a High Performance Front-End Radar Signal Processor

Journal of VLSI Signal Processing Systems
On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays

IEEE Transactions on Parallel and Distributed Systems
FPGA in the software radio

IEEE Communications Magazine
Frame-level pipelined motion estimation array processor

IEEE Transactions on Circuits and Systems for Video Technology
A novel modular systolic array architecture for full-search block matching motion estimation

IEEE Transactions on Circuits and Systems for Video Technology

Quantified Score

Hi-index	0.00

Visualization

Abstract

The consolidation of Internet devices into a universal/portable device will soon be accomplishable through the incorporation of reconfigurable computing in system-on-a-chip (SOC). At any particular moment, it could be a video/audio mobile phone, an MP3 song player, and other devices. The basic construct of these multimedia processing algorithms can be described as deep nested Do loop algorithms. They are considered the most demanding data-intensive algorithms and hence ideal candidates for an array of reconfigurable nanoprocessors. Therefore, algorithm to hardware synthesis methodology is important for an efficient exploitation of both spatial parallelism and temporal pipelining. In this paper, we propose a processor array synthesis methodology. It can map an n-level nested Do loop represented by a nonuniform or shift-variant data dependence graph to a near-optimal of one-or two-dimensional processor array under the available resource constraints to satisfy high-throughput computation demands.