Implementing a RAKE receiver for wireless communications on an FPGA-based computer system
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Digit-Serial Complex-Number Multipliers on FPGAs
Journal of VLSI Signal Processing Systems
Processor Array Synthesis from Shift-Variant Deep Nested Do Loops
The Journal of Supercomputing
Reconfigurable Systems: New Activities in Asia
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Software Radio Reconfigurable Hardware System (SHaRe)
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
High Performance Quadrature Digital Mixers for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A reconfigurable, power-scalable rake receiver IP for W-CDMA
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
FPGA-based reconfigurable measurement instruments with functionality defined by user
EURASIP Journal on Applied Signal Processing
Low complexity radix-4 butterfly design for the soft-decision Viterbi decoder
Microprocessors & Microsystems
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
Integration, the VLSI Journal
Superscalar architecture design for high performance DSP operations
Microprocessors & Microsystems
Efficient communication between the embedded processor and the reconfigurable logic on an FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parametric Design for Reconfigurable Software-Defined Radio
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Sora: high performance software radio using general purpose multi-core processors
NSDI'09 Proceedings of the 6th USENIX symposium on Networked systems design and implementation
Sora: high-performance software radio using general-purpose multi-core processors
Communications of the ACM
Reduced-precision redundancy on FPGAs
International Journal of Reconfigurable Computing
Cognitive computing resource management for a ubiquitous wireless access
UIC'07 Proceedings of the 4th international conference on Ubiquitous Intelligence and Computing
Cognitive Aeronautical Communication System
International Journal of Interdisciplinary Telecommunications and Networking
Reconfigurable pipelined coprocessor for multi-mode communication transmission
Proceedings of the 50th Annual Design Automation Conference
Software radio on smartphones: feasible?
Proceedings of the 15th Workshop on Mobile Computing Systems and Applications
| Hi-index | 0.27 |
As new radio standards are deployed without substantially supplanting existing ones, the need for multimode multiband handsets and infrastructure increases. This article describes how emerging FPGA technology's unique combination of size and power efficiency plus field programmability offers a transition of FPCAs from ASIC prototyping to embedded products. Software-defined receiver examples suggest an enlarged role for FPGAs in pragmatic paths toward the productization of software radio technology