picoArray Technology: The Tool's Story
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Measuring the gap between FPGAs and ASICs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
Software defined radio in the electrical and computer engineering curriculum
FIE'09 Proceedings of the 39th IEEE international conference on Frontiers in education conference
Parallel implementation of convolution encoder for software defined radio on DSP architecture
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
A Rapid Methodology for Multi-mode Communication Circuit Generation
VLSID '12 Proceedings of the 2012 25th International Conference on VLSI Design
IEEE Communications Magazine
Efficient datapath merging for partially reconfigurable architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping
VLSID '13 Proceedings of the 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems
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The need to integrate multiple wireless communication protocols into a single low-cost, low-power hardware platform is prompted by the increasing number of emerging communication protocols and applications. This paper presents a novel application specific platform for integrating multiple wireless communication transmission baseband protocols in a pipelined coprocessor, which can be programmed to support various baseband protocols. This coprocessor can dynamically select the suitable pipeline stages for each baseband protocol. Moreover, each carefully designed stage is able to perform a certain signal processing function in a reconfigurable fashion. The proposed platform is flexible (compared to ASICs) and is suitable for mobile applications (compared to FPGAs and processors). The area footprint of the coprocessor is smaller than an ASIC or FPGA implementation of multiple individual protocols, while the overhead of throughput is 34% worse than ASICs and 32% better than FPGAs. The power consumption is 2.7X worse than ASICs but 40X better than FPGAs on average. The proposed platform outperforms processor implementation in all area, throughput and power consumption. Moreover, fast protocol switching is supported. Wireless LAN (WLAN) 802.11a, WLAN 802.11b and Ultra Wide Band (UWB) transmission circuits are developed and mapped to the pipelined coprocessor to prove the efficacy of our proposal.