Multirate Digital Signal Processing
Multirate Digital Signal Processing
Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing
Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing
The CORDIC Algorithm: New Results for Fast VLSI Implementation
IEEE Transactions on Computers
Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors
IEEE Transactions on Computers
IEEE Communications Magazine
Complexity of a software GSM base station
IEEE Communications Magazine
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Wireless communication systems operate within a wide variety of dynamic ranges, variable bandwidths and carrier frequencies. New high density re-programmable logic arrays are a suitable technology basis providing sufficient processing power required by software radio concepts employing multiple standards and transmission schemes. For high speed wireless data transmission and access networks as used in multimedia communication systems fast signal synchronization and acquisition schemes are required. Within this work, programmable carrier phase synchronization units have been designed as FPGA based subsystems to be used in various re-configurable digital receiver concepts. The performance and the available processing capacity was investigated and verified within a rapid prototyping design flow environment.