Efficient communication between the embedded processor and the reconfigurable logic on an FPGA

Authors:
Joshua Noseworthy;Miriam Leeser
Affiliations:
Mercury Computer Systems, Chelmsford, MA and Northeastern University, Boston, MA;Department of Electrical and Computer Engineering, Northeastern University, Boston, MA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

Citing 2
Cited 1

Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro

FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
FPGA in the software radio

IEEE Communications Magazine

Integrating real-time inter-task communication channels into hardware-software codesign

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Increasing device densities have prompted FPGA manufacturers, such as Xilinx and Altera, to incorporate larger embedded components, including multipliers, DSP blocks and even embedded processors. One of the recent architectural enhancements in the Xilinx Virtex family architecture is the introduction of the PowerPC405 hard-core embedded processor. In this paper we present a Software Defined Radio application that serves as a vehicle for investigating effective communication between the PowerPC405 processor and the surrounding FPGA fabric. A challenging aspect of developing applications that target the PowerPC is the interfacing of the processor with the surrounding reconfigurable logic. We have implemented a dozen different versions of a Software Defined Radio (SDR) application to exercise the various interfaces that enable communication between the processor and the surrounding FPGA fabric. The implementations differ only in the interfaces used. Our results indicate that the performance of the SDR application can be increased by as much as 60 percent just by choosing the interfaces that are most appropriate for the different types of data in the implementation. This demonstrates that the performance of FPGA applications that use the embedded processor are dramatically affected by the mechanisms chosen to enable communication between the processor and its surrounding resources. The best implementations use all of the different interfaces; this makes the best use of the bandwidth available to the PowerPC core.