IEEE Transactions on Computers
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Proceedings of the 27th annual international symposium on Computer architecture
Re-configurable computing in wireless
Proceedings of the 38th annual Design Automation Conference
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Cache Optimization For Embedded Processor Cores: An Analytical Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Cache Optimization for Mobile Devices Running Multimedia Applications
ISMSE '04 Proceedings of the IEEE Sixth International Symposium on Multimedia Software Engineering
Configuration Steering for a Reconfigurable Superscalar Processor
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Fast branch misprediction recovery in out-of-order superscalar processors
Proceedings of the 19th annual international conference on Supercomputing
Software-defined radio: basics and evolution to cognitive radio
EURASIP Journal on Wireless Communications and Networking
Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations
IEEE Transactions on Computers
Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning
DSN '07 Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
IEEE Communications Magazine
A soft radio architecture for reconfigurable platforms
IEEE Communications Magazine
A PC-based software receiver using a novel front-end technology
IEEE Communications Magazine
Architecture level design space exploration of superscalar processor for multimedia applications
SPECTS'09 Proceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems
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This paper evaluates the possibility of using a general purpose superscalar architecture as the main computational engine for high performance DSP algorithms. Real-time sample rate conversion (SRC) in a software defined radio (SDR) has been taken as an example representing a class of computationally demanding DSP tasks. This scenario corresponds to digital filters operating at a high sampling rate in intermediate frequency (IF) stage of a multi-standard wireless transceiver. However, instead of a dedicated signal processing engine, a superscalar processor is designed for SRC implementation. An iterative, SimpleScalar based architectural modeling tool has been developed to analyze various parameters of superscalar processors. Both power and performance metrics have been taken under consideration to come up with an efficient design. It has been shown that the resulting superscalar architecture can provide a fully programmable solution capable of supporting future wireless communication standards in real-time. The design methodology explored in this work can be extended to obtain efficient processor architectures for a range of other applications.