Cache modeling and optimization for portable devices running MPEG-4 video decoder
Multimedia Tools and Applications
Superscalar architecture design for high performance DSP operations
Microprocessors & Microsystems
Intelligent prebuffering using position oriented database for mobile devices
ACIIDS'10 Proceedings of the Second international conference on Intelligent information and database systems: Part I
Problem solving of low data throughput on mobile devices by artefacts prebuffering
EURASIP Journal on Wireless Communications and Networking - Special issue on enabling Wireless Technologies for Green Pervasive Computing
Memory architecture evaluation for video encoding on enhanced embedded processors
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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The popularity of mobile/wireless embedded systems running multimedia applications is growing. MPEG4 is an important and demanding multimedia application. With improved CPU, memory subsystem deficiency is the major barrier to improving the system performance. Studies show that there is sufficient reuse of values for caching to significantly reduce the raw required memory bandwidth for video data. Decoding MPEG4 video data in software generates many times more cache-memory traffic than required. Proper understanding of the decoding algorithm and the composition of its data set is obvious to improve the performance of such a system. The focus of this paper is to enhance MPEG4 decoding performance through cache optimization of a mobile device. The architecture we simulate includes a digital signal processor (DSP) to run the decoding algorithm and a two-level cache system. Level-1 cache is split into Data (D1) and Instruction (I1) caches and level-2 (CL2) is a unified cache. We use Cachegrind and VisualSim simulation tools to optimize cache size, line size, associativity, and levels of caches for a wireless device decoding MPEG4 video.