Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Performance of H.26L Video Encoder on General-Purpose Processor
Journal of VLSI Signal Processing Systems
Media Processing Applications on the Imagine Stream Processor
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Evaluation of SIMD Architecture Enhancement in Embedded Processors for MPEG-4
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Cache Optimization for Mobile Devices Running Multimedia Applications
ISMSE '04 Proceedings of the IEEE Sixth International Symposium on Multimedia Software Engineering
HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing
Journal of VLSI Signal Processing Systems
An MPEG-4 performance study for non-SIMD, general purpose architectures
ISPASS '03 Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software
High-performance arithmetic coding VLSI macro for the H264 video compression standard
IEEE Transactions on Consumer Electronics
A multi-standard video accelerator based on a vector architecture
IEEE Transactions on Consumer Electronics
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture
IEEE Transactions on Circuits and Systems for Video Technology
Overview of research efforts on media ISA extensions and their usage in video coding
IEEE Transactions on Circuits and Systems for Video Technology
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In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. The memory architecture is integrated with SIMD extended embedded processor, proposed in our previous work. We explore both dedicated memories and multilevel cache architectures and perform exhaustive simulations. The simulations have been conducted using highly optimized proprietary video encoding code for mobile handheld devices. Our simulation results show that the performance improvement of dedicated memories on video encoding applications is not very significant. The multilevel cache-based architecture processes approximately 17 frames/s compared to 19-22 frames/s for 512 KB dedicated on-chip zero-wait state memory. Thus it is difficult to justify using dedicated memory for this kind of embedded systems, when energy consumption and cost of implementation are also considered.