HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing

  • Authors:

  • Hans-Joachim Stolberg;Mladen Bereković;Sören Moch;Lars Friebe;Mark B. Kulaczewski;Sebastian Flügel;Heiko Kluβmann;Andreas Dehnhardt;Peter Pirsch

  • Affiliations:

  • Institute of Microelectronic Systems, University of Hannover, Hannover, Germany 30167;Institute of Microelectronic Systems, University of Hannover, Hannover, Germany 30167;Institute of Microelectronic Systems, University of Hannover, Hannover, Germany 30167;Institute of Microelectronic Systems, University of Hannover, Hannover, Germany 30167;Institute of Microelectronic Systems, University of Hannover, Hannover, Germany 30167;Institute of Microelectronic Systems, University of Hannover, Hannover, Germany 30167;Institute of Microelectronic Systems, University of Hannover, Hannover, Germany 30167;Institute of Microelectronic Systems, University of Hannover, Hannover, Germany 30167;Institute of Microelectronic Systems, University of Hannover, Hannover, Germany 30167

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2005

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Abstract

The HiBRID-SoC multi-core system-on-chip architecture targets a wide range of multimedia applications with particularly high processing demands, including general signal processing applications, video de-/encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 驴m 6LM standard-cell CMOS technology, occupies about 81 mm2, and operates at 145 MHz. An MPEG-4 Advanced Simple Profile decoder in full D1 resolution requires about 120 MHz for real-time operation on the HiBRID-SoC, utilizing only two of the three cores. Together with the third core, a custom region-of-interest (ROI) based surveillance application can be built.