Journal of VLSI Signal Processing Systems - Special issue: video/image signal processing
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
Subword Parallelism with MAX-2
IEEE Micro
An Architectural Overview of the Programmable Multimedia Processor, TM-1
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Image and video coding-emerging standards and beyond
IEEE Transactions on Circuits and Systems for Video Technology
VLSI implementations of image and video multimedia processing systems
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
Reconfigurable repetitive padding unit
Proceedings of the 12th ACM Great Lakes symposium on VLSI
System-Level Analysis for MPEG-4 Decoding on a Multi-Processor Architecture
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
A 2D Addressing Mode for Multimedia Applications
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Processor Architectures for Multimedia Applications
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Processor architectures for multimedia applications
Embedded processor design challenges
A 2D addressing mode for multimedia applications
Embedded processor design challenges
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
HIBRID-SOC: a multi-core architecture for image and video applications
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
A scalable, clustered SMT processor for digital signal processing
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
Matrix register file and extended subwords: two techniques for embedded media processors
Proceedings of the 2nd conference on Computing frontiers
HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems
An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System
Journal of VLSI Signal Processing Systems
A novel configurable motion estimation architecture for high-efficiency MPEG-4/H.264 encoding
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Avoiding conversion and rearrangement overhead in SIMD architectures
International Journal of Parallel Programming
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Profiling-based hardware/software co-exploration for the design of video coding architectures
IEEE Transactions on Circuits and Systems for Video Technology
Polymorphic architectures: from media processing to supercomputing
CompSysTech '09 Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
A heterogeneous embedded MPSoC for multimedia applications
HPCC'06 Proceedings of the Second international conference on High Performance Computing and Communications
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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This paper describes instruction set extensions for theacceleration of MPEG-4 algorithms on programmable (RISC-) CPUs. MPEG-4 standardizes audio and video compression schemes for a varietyof bit rates and scenarios. As MPEG-4 targets a much broader range ofdifferent applications than previously defined hybrid video codingstandards like H.263 or MPEG-2, it employs a much higher number ofdifferent algorithms and coding modes. Therefore, MPEG-4implementations will require a more software-oriented approach to beefficient. However, the total computational load for an optimizedimplementation of an MPEG-4 video codec is expected to exceed theperformance levels of today's multimedia signal processors, makingfurther hardware acceleration a necessity. For that purpose, wepropose a number of instruction set extensions that addfunction-specific blocks to the data path of a CPU. These dedicatedmodules are highly adapted to the most computation-intensiveprocessing schemes of MPEG-4, such as DCT, motion compensation,padding, shape coding, or bitstream parsing. The increasedfunctionality of basic instructions results in a significant speed-upover standard RISC instruction sets, thus making MPEG-4implementations feasible on programmable processor platforms. Possible target architectures include VLIW multimedia processors,MIMD-style multiprocessors, or coprocessorarchitectures