A heterogeneous embedded MPSoC for multimedia applications

  • Authors:

  • Hong Yue;Zhiying Wang;Kui Dai

  • Affiliations:

  • College of Computer, National University of Defense Technology, Changsha, Hunan, P.R.China;College of Computer, National University of Defense Technology, Changsha, Hunan, P.R.China;College of Computer, National University of Defense Technology, Changsha, Hunan, P.R.China

  • Venue:
  • HPCC'06 Proceedings of the Second international conference on High Performance Computing and Communications
  • Year:
  • 2006

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Abstract

MPSoC are attractive candidate architectures for multimedia processing as multimedia schemes generally can be partitioned in control-oriented and data-dominated functions, which can all be processed in parallel on different cores. This paper presents a heterogeneous embedded MPSoC for a wide range of application fields with particularly high processing demands. It integrates three processor cores and various interfaces onto a single chip, all tied to a 32-bit AMBA AHB bus. The RISC core coordinates the system and performs some reactive tasks, and the cluster composed by two DSP cores perform transformational tasks with more deterministic and regular behaviors, such as the small and well-defined workloads in multimedia signal processing applications. The DSP cores are designed based on Transport Triggered Architecture (TTA) to reduce hardware complexity, get high flexibility and shorten market time. The processor is fabricated in 0.18um standard-cell technology, occupies about 21.4mm2, and operates at 266MHz while consuming 870mW average power.