The MPEG-4 Multimedia Coding Standard: Algorithms, Architectures and Applications
Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
Instruction Set Extensions for MPEG-4 Video
Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
March tests for word-oriented memories
Proceedings of the conference on Design, automation and test in Europe
March Tests for Realistic Faults in Two-Port Memories
MTDT '00 Proceedings of the 2000 IEEE International Workshop on Memory Technology, Design and Testing
18.2 Fault Models and Tests for Two-Port Memories
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
Architecture for video coding on a processor with an ARM and DSP cores
Multimedia Tools and Applications
A heterogeneous embedded MPSoC for multimedia applications
HPCC'06 Proceedings of the Second international conference on High Performance Computing and Communications
A distributed architecture model for heterogeneous multiprocessor system-on-chip design
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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The HiBRID-SoC multi-core system-on-chip targets a wide range of application fields with particularly high processing demands, including general signal processing applications, video and audio de-/encoding, and a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 µm 6LM standard-cell technology, occupies about 82 mm2 , and operates at 145 MHz.