Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Testing complex couplings in multiport memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Simulation-based test algorithm generation and port scheduling for multi-port memories
Proceedings of the 38th annual Design Automation Conference
Efficient Tests for Realistic Faults in Dual-Port SRAMs
IEEE Transactions on Computers
Consequences of port restrictions on testing two-port memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A new framework for generating optimal March tests for memory arrays
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Address Decoder Faults and their Tests for Two-Port Memories
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
BITLINE CONTACTS IN HIGH DENSITY SRAMS: DESIGN FOR TESTABILITY AND STRESSABILITY
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Port Interference Faults in Two-Port Memories
ITC '99 Proceedings of the 1999 IEEE International Test Conference
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs
Journal of Electronic Testing: Theory and Applications
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In this paper the effcts of simultaneous memory access on the fault modeling for two-port memories are investigated. New fault models and their march tests are presented. The obtained tests are of order O(n2), which makes them less practical for larger two-port memories. However, the complexity can be reduced to O(n), when the memory topology is taken into account.