Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy

Authors:
Said Hamdioui;Ad J. Van De Goor
Affiliations:
Intel Corporation, 2200 Mission College Boulevard, Santa Clara, CA 95052, USA. said@cardit.et.tudelft.nl;Delft University of Technology, Faculty of Information Technology and Systems, Section of Computer Architecture and Digital Technology, P.O. Box 5031, 2600 GA Delft, The Netherlands. vdGo ...
Venue:
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Year:
2000

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Abstract

This paper describes a novel method that can be used to reduce test cycle count in a parallel access scan based Built-In-Self-Test (BIST) environment. An algorithm that allows the efficient application of deterministically generated patterns is proposed. ...