An Effective BIST Scheme for ROM's
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Programmable BIST Space Compactors
IEEE Transactions on Computers
Scalable Test Generators for High-Speed Datapath Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
An effective BIST architecture for fast multiplier cores
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An Effective Built-In Self-Test Scheme for Parallel Multipliers
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Self-adjusting output data compression: an efficient BIST technique for RAMs
Proceedings of the conference on Design, automation and test in Europe
Processor-programmable memory BIST for bus-connected embedded memories
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
Journal of Electronic Testing: Theory and Applications
Efficient Tests for Realistic Faults in Dual-Port SRAMs
IEEE Transactions on Computers
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Effective Built-In Self-Test for Booth Multipliers
IEEE Design & Test
A Programmable BIST Core for Embedded DRAM
IEEE Design & Test
Design and Test of Large Embedded Memories: An Overview
IEEE Design & Test
Efficient Online and Offline Testing of Embedded DRAMs
IEEE Transactions on Computers
Consequences of port restrictions on testing two-port memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Detection of CMOS address decoder open faults with March and pseudo random memory tests
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An efficient BIST method for distributed small buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Unified scan design with scannable memory arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
An effective BIST design for PLA
ATS '95 Proceedings of the 4th Asian Test Symposium
Address Decoder Faults and their Tests for Two-Port Memories
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Converting March Tests for Bit-Oriented Memories Into Tests for Word-Oriented Memories
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Verification of CAM Tests for Input Stuck-at Faults
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Disturb Neighborhood Pattern Sensitive Fault
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
18.2 Fault Models and Tests for Two-Port Memories
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
An Efficient BIST Method for Small Buffers
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Error Detecting Refreshment for Embedded DRAMs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Shadow Write and Read For At-Speed BIST Of TDM SRAMs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Highly-Efficient Transparent Online Memory Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
An Effective BIST Scheme for Arithmetic Logic Un i t s
ITC '97 Proceedings of the 1997 IEEE International Test Conference
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Port Interference Faults in Two-Port Memories
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs
Journal of Electronic Testing: Theory and Applications
Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing
IEEE Transactions on Computers
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Opens and Delay Faults in CMOS RAM Address Decoders
IEEE Transactions on Computers
Extending boundary-scan to perform a memory built-in self-test
ICC'05 Proceedings of the 9th International Conference on Circuits
Fault models for embedded-DRAM macros
Proceedings of the 46th Annual Design Automation Conference
An effective BIST scheme for ring-address type FIFOs
ITC'94 Proceedings of the 1994 international conference on Test
Efficient O(√n ) BIST algorithms for DDNPS faults in dual port memories
ITC'94 Proceedings of the 1994 international conference on Test
Testing methodology of embedded DRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A serial interfacing scheme in which several embedded memories share the built-in, self-test circuit is presented. For external testing, this approach requires only two serial pins for access to the data path. There is considerable savings in routing area, and fewer external pins are needed to test random-access memories with wide words, such as those in application-specific integrated circuits for telecommunications. Even though the method uses serial access to the memory, a test pattern is applied every clock cycle because the memory itself shifts the test data. The method has been adapted to four common algorithms. In implementations of built-in self-test circuitry on several product chips, the area overhead was found to be acceptable.