Efficient O(√n ) BIST algorithms for DDNPS faults in dual port memories

Authors:
A. A. Amin;M. Y. Osman;R. E. Abdel-Aal;H. Al-Muhtaseb
Affiliations:
Computer Engineering Department, King Fahd University of Petroleum and Minerals, Saudi Arabia;Computer Engineering Department, King Fahd University of Petroleum and Minerals, Saudi Arabia;Energy Research Laboratory of the Research Institute, King Fahd University of Petroleum and Minerals, Saudi Arabia;Information and Computer Science Department, King Fahd University of Petroleum and Minerals, Saudi Arabia and
Venue:
ITC'94 Proceedings of the 1994 international conference on Test
Year:
1994

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Abstract

The testability problem of dual port memories is investigated. Architectural modifcations which enhance testability with minimal overhead on both silicon area and device performance are described. New fault models for both the memory array and the address decoders are proposed and eficient O(√n) test algorithms are presented. The new fault models account for the simultaneous dual access property of the device. In addition to the classical static neighborhood pattern sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, Duplex Dynamic Neighborhood Pattern Sensitive faults (PDNPSF).