An effective BIST scheme for ring-address type FIFOs

Authors:
Yervant Zorian;Ad J. Van de Goor;Ivo Schanstra
Affiliations:
AT&T Bell Laboratories, Princeton, NJ;Delft University of Technology, Department of Electrical Engineering, Delft, The Netherlands;Delft University of Technology, Department of Electrical Engineering, Delft, The Netherlands
Venue:
ITC'94 Proceedings of the 1994 international conference on Test
Year:
1994

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Abstract

FIFO memories impose special test problems because of their built-in addressing restrictions and access limitations. With the increasing usage of FIFOs today, generic algorithms are needed to test stand-alone FIFO chips and embedded FIFO macros. This paper addresses the problem of testing a very popular type of FIFO, namely the ring-address FIFO. It introduces two novel algorithms to test this type of FIFO. Both algorithms provide full fault coverage for a comprehensive fault model. The first algorithm uses a generic test approach in the sense that it does not require any change to the FIFO hardware. Whereas, the second algorithm is DFT-based. It assumes access to a FIFO design and suggests minor DFT modifications, in order to reduce the test complexity from O(n2) to O(n). The BIST architecture of the DFT-based algorithm, which has recently been utilized in different products, is also described.