A Parametric Design of a Built-in Self-Test FIFO Embedded Memory
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Path-RO: a novel on-chip critical path delay measurement under process variations
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Analysis of Resistive Bridging Defects in a Synchronizer
ATS '09 Proceedings of the 2009 Asian Test Symposium
Analysis of Resistive Open Defects in a Synchronizer
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer
Journal of Electronic Testing: Theory and Applications
An effective BIST scheme for ring-address type FIFOs
ITC'94 Proceedings of the 1994 international conference on Test
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This paper presents a test method for testing two-D-flip-flop synchronizers in an asynchronous first-in-first-out (FIFO) interface. A faulty synchronizer can have different fault behaviors depending on the input application time, the fault location, the fault mechanism, and the applied clock frequency. The proposed test method can apply the input patterns at different time and generate capture clock signals with different frequency regardless of phase-locked loop (PLL) of the design. To implement the proposed test method, channel delay compensator, delayed scan enable signal generator, launch clock generator, and capture clock generator are designed. In addition, a well-designed calibration method is proposed to calibrate all programmable delay elements used in the test circuits. The proposed test method evolves to several test sections to detect all possible faults of the two-D-flip-flop synchronizers in the asynchronous FIFO interface.