Oscillation Ring Delay Test for High Performance Microprocessors
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
All digital built-in delay and crosstalk measurement for on-chip buses
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the IEEE International Test Conference 2001
Facilitating Rapid First Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On-chip delay measurement for silicon debug
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A Scheme for On-Chip Timing Characterization
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Testing On-Die Process Variation in Nanometer VLSI
IEEE Design & Test
Design for Manufacturability and Statistical Design: A Comprehensive Approach
Design for Manufacturability and Statistical Design: A Comprehensive Approach
A Production IR-Drop Screen on a Chip
IEEE Design & Test
Low-overhead design technique for calibration of maximum frequency at multiple operating points
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adjustment-based modeling for timing analysis under variability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations
Proceedings of the 47th Design Automation Conference
Representative path selection for post-silicon timing prediction under variability
Proceedings of the 47th Design Automation Conference
Optimal statistical chip disposition
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the great lakes symposium on VLSI
Testing of Synchronizers in Asynchronous FIFO
Journal of Electronic Testing: Theory and Applications
SlackProbe: a low overhead in situ on-line timing slack monitoring methodology
Proceedings of the Conference on Design, Automation and Test in Europe
An on-chip delay measurement technique using signature registers for small-delay defect detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-precision on-chip path delay measurement architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A sensor-assisted self-authentication framework for hardware trojan detection
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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As technology scales to 45nm and below, process variations will present significant impact on path delay. This trend makes the deviation between simulated path delay and actual path delay in a manufactured chip more significant. In this paper, we propose a new on-chip path delay measurement structure called path-based ring oscillator (Path-RO). The proposed method creates an oscillator from a targeted path for which it is used to measure path delay on-chip under the impact of process variations. To alleviate accuracy degradation caused by the architecture itself, a high-accuracy calibration process is presented. Through experimental results on Path-ROs inserted in ITC'99 b19 benchmark, we obtain path delay distribution under different process variations. The accuracy and efficiency of path delay measurement using Path-RO are also verified by comparing the results obtained from post-layout Hspice simulations.