Overview of gate linewidth control in the manufacture of CMOS logic chips
IBM Journal of Research and Development - Special issue: IBM CMOS technology
On-Chip Structures for Timing Measurements and Test
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Low-overhead design technique for calibration of maximum frequency at multiple operating points
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Within-die process variations: how accurately can they be statistically modeled?
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Path-RO: a novel on-chip critical path delay measurement under process variations
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
At-speed delay characterization for IC authentication and Trojan Horse detection
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the 48th Design Automation Conference
Hardware Trojans in wireless cryptographic ICs: silicon demonstration & detection method evaluation
Proceedings of the International Conference on Computer-Aided Design
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As feature printability becomes more challenging in advanced technology nodes, measuring and characterizing process variation effects on delay and power is becoming increasingly important. In this paper, we present two embedded test structures (ETS) for carrying out path delay measurement in actual product designs. Of the two structures proposed here, one is designed to be incorporated into a customer's scan structures, augmenting selected functional units with the ability to perform accurate path delay measurements. We refer to this ETS as REBEL (regional delay behavior). It is designed to leverage the existing scan chain as a means of reducing area overhead and performance impact. For cases in which very high resolution of delay measurements is required, a second standalone structure is proposed which we refer to as TDC for time-to-digital converter. Beyond characterizing process variations, these ETSs can also be used for design debug, detection of hardware Trojans and small delay defects and as physical unclonable functions.