Low-overhead design technique for calibration of maximum frequency at multiple operating points

Authors:
Somnath Paul;Sivasubramaniam Krishnamurthy;Hamid Mahmoodi;Swarup Bhunia
Affiliations:
Case Western Reserve University, Cleveland, OH;Case Western Reserve University, Cleveland, OH;San Francisco State University, CA;Case Western Reserve University, Cleveland, OH
Venue:
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Year:
2007

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Abstract

Determination of maximum operating frequencies (Fmax) during manufacturing test at different operating voltages is required to: (a) to ensure that, for a Dynamic Voltage and Frequency Scaling (DVFS) system, the adaptation hardware actually applies the correct operating frequency corresponding to a scaled supply and (b) to sort chips in different voltage-frequency (V-Fmax)bins, so that chips at different bins can be used for different applications. Existing speed binning approach requires extensive delay testing at all operating points with all possible frequencies, which increases test cost and test time significantly. In this paper, we propose a low-overhead solution for characterizing Fmax of a circuit at different operating voltages that can eliminate the complex and expensive Fmax calibration at multiple voltage points. The basic idea is to choose a small set of representative paths in a circuit based on their voltage sensitivity and dynamically configuring them into ring oscillator to compute the Fmax. The proposed calibration mechanism is all-digital, robust to process variations, reasonably accurate (average 2.8% error) and incorporates minimal hardware overhead (average 1.7% delay, 3.5% area and 0.28% power overhead).