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DAC '97 Proceedings of the 34th annual Design Automation Conference
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Proceedings of the 37th Annual Design Automation Conference
Analysis and optimization of thermal issues in high-performance VLSI
Proceedings of the 2001 international symposium on Physical design
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal resilient bounded-skew clock tree optimization methodology
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Dynamic thermal clock skew compensation using tunable delay buffers
Proceedings of the 2006 international symposium on Low power electronics and design
Minimal skew clock embedding considering time variant temperature gradient
Proceedings of the 2007 international symposium on Physical design
Thermally robust clocking schemes for 3D integrated circuits
Proceedings of the conference on Design, automation and test in Europe
Integration, the VLSI Journal
Low-overhead design technique for calibration of maximum frequency at multiple operating points
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Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
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Buffered clock tree synthesis for 3D ICs under thermal variations
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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Proceedings of the 18th ACM Great Lakes symposium on VLSI
Dynamic thermal clock skew compensation using tunable delay buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Design of thermally robust clock trees using dynamically adaptive clock buffers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Thermal-aware clock tree design to increase timing reliability of embedded SoCs
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Buffered clock tree sizing for skew minimization under power and thermal budgets
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock tree embedding for 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
SACTA: a self-adjusting clock tree architecture for adapting to thermal-induced delay variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic management of thermally-induced clock skew: an implementation perspective
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Fast timing analysis of clock networks considering environmental uncertainty
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Integration, the VLSI Journal
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper, an efficient linear time algorithm TACO is proposed for the first time to minimize the worst case clock skew in the presence of on-chip thermal variation. TACO, while tries to minimize the worst case clock skew, also attempts to minimize the clock tree wirelength by building up merging diamonds in a bottom-up manner. As an output, TACO provides balanced merging points and the modified clock routing paths to minimize the worst case clock skew under thermal variation. Experimental results on a set of standard benchmarks show 50-70% skew reduction with less than 0.6% wirelength overhead.