Clock routing for high-performance ICs
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A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Practical Bounded-Skew Clock Routing
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
More practical bounded-skew clock routing
DAC '97 Proceedings of the 34th annual Design Automation Conference
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fabrication Technologies for Three-Dimensional Integrated Circuits
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Minimizing peak current via opposite-phase clock tree
Proceedings of the 42nd annual Design Automation Conference
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Temperature-aware routing in 3D ICs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
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ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
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Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 44th annual Design Automation Conference
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ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
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Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Buffered clock tree synthesis for 3D ICs under thermal variations
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
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Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Process-induced skew variation for scaled 2-D and 3-D ICs
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
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Proceedings of the 47th Design Automation Conference
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Proceedings of the 16th Asia and South Pacific Design Automation Conference
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Proceedings of the 49th Annual Design Automation Conference
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ACM Journal on Emerging Technologies in Computing Systems (JETC)
TSV array utilization in low-power 3D clock network design
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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Proceedings of the International Conference on Computer-Aided Design
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This paper addresses a fundamental problem of zero skew clock tree embedding problem in 3D ICs. We propose an algorithm, called ZCTE-3D, for solving the zero skew clock tree embedding problem in 3D ICs for a given tree topology. The primary objective is to minimize the cost of TSVs together with finding embedding layers and the secondary objective is to minimize the cost of wirelength. We show that ZCTE-3D solves the problem optimally in polynomial time under the linear delay model, while it solves the problem suboptimally under the Elmore delay model. We also propose an effective 3D clock tree synthesis flow by integrating a multi-layer tree topology generation algorithm, called MMM-3D, into ZCTE-3D. Through an extensive exploitation of ZCTE-3D in experiments, we have analyzed the relation between the number of TSVs, the total wirelength, and tree topology. When compared with the results produced by the previous 3D clock tree synthesis algorithm BURITO, experimental results show that ZCTE-3D uses on average 10% less number of TSVs with similar wirelength and delay for the same tree topologies. Furthermore, by generating tree topologies with MMM-3D, we are able to reduce the number of TSVs by 10% on average even with 4% shorter wirelength and 2% reduced delay.