2.5D system integration: a design driven system implementation schema
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Implementing Caches in a 3D Technology for High Performance Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Three-dimensional place and route for FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Thermal analysis of a 3D die-stacked high-performance microprocessor
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Scalability of 3D-integrated arithmetic units in high-performance microprocessors
Proceedings of the 44th annual Design Automation Conference
Buffered clock tree synthesis for 3D ICs under thermal variations
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Parametric yield management for 3D ICs: Models and strategies for improvement
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Scan-chain design and optimization for three-dimensional integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Is 3D chip technology the next growth engine for performance improvement?
IBM Journal of Research and Development
The impact of liquid cooling on 3D multi-core processors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Clock tree embedding for 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock Tree synthesis for TSV-based 3D IC designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Microelectronic Engineering
Spatial and temporal thermal characterization of stacked multicore architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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The MIT approach to 3-D VLSI integration is based on low-temperature Cu-Cu wafer bonding. Device wafers are bonded in a face-to-back manner, with short vertical vias and Cu-Cu pads as the inter-wafer throughway. In our scheme, there are several reliability criteria, which include: a) Structural integrity of the Cu-Cu bond, b) Cu-Cu contact electrical characteristics, and c) Process flow efficiency and repeatability. In addition, CAD tools are needed to aid in design and layout of 3DICs. This paper will discuss recent results in all these areas.