Review Article: Wafer-level three-dimensional integrated circuits (3D IC): Schemes and key technologies

Authors:
Ming-Fang Lai;Shih-Wei Li;Jian-Yu Shih;Kuan-Neng Chen
Affiliations:
Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan;Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan;Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan;Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
Venue:
Microelectronic Engineering
Year:
2011

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Fabrication Technologies for Three-Dimensional Integrated Circuits

ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design

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Abstract

Schemes and key technologies of wafer-level three-dimensional integrated circuits (3D IC) are reviewed and introduced in this paper. Direction of wafer stacking, methods of wafer bonding, fabrication of through-silicon via (TSV), and classification of wafer type are options for 3D IC schemes. Key technologies, such as alignment, Cu bonding, and TSV fabrication, are described as well. Better performance, lower cost, and more functionality of future electronic products become feasible with 3D IC concept application.