Prospects for WSI: A Manufacturing Perspective
Computer - Special issue on wafer-scale integration
Smart-Substrate Multichip-Module Systems
IEEE Design & Test
Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
Performance driven multi-layer general area routing for PCB/MCM designs
DAC '98 Proceedings of the 35th annual Design Automation Conference
VLSI design in the 3rd dimension
Integration, the VLSI Journal
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Power simulation and estimation in VLSI circuits
The VLSI handbook
The next chip challenge: effective methods for viable mixed technology SoCs
Proceedings of the 39th annual Design Automation Conference
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Using Partial Isolation Rings to Test Core-Based Designs
IEEE Design & Test
Future System-on-Silicon LSI Chips
IEEE Micro
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
Proceedings of the IEEE International Test Conference
Design of Reconfigurable Access Wrappers for Embedded Core Based SOC Test
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Fabrication Technologies for Three-Dimensional Integrated Circuits
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Testing a System-On-a-Chip with Embedded Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Silicon VLSI Technology
Three-Dimensional Cache Design Exploration Using 3DCacti
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Implementing Caches in a 3D Technology for High Performance Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Optimal topology exploration for application-specific 3D architectures
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Dynamic instruction schedulers in a 3-dimensional integration technology
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
SOC'09 Proceedings of the 11th international conference on System-on-chip
Invited paper: Thermal modeling and analysis of 3D multi-processor chips
Integration, the VLSI Journal
SEC'13 Proceedings of the 22nd USENIX conference on Security
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This paper investigates a 3D die-stacking based VLSI integration strategy, so-called 2.5D integration, which can potentially overcome many problems stumbling the development of monolithic System-on-Chip (SoC). In this paper, we review available fabrication technologies and testing solutions for the new integration strategy. We also propose a design driven system implementation schema for this new integration strategy. A layout synthesis framework is under development by us to analyze typical "what if" questions and resolve major physical attributes for a 2.5D system according to the design specification and constraints.