Prospects for WSI: A Manufacturing Perspective
Computer - Special issue on wafer-scale integration
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
Interconnect characteristics of 2.5-D system integration scheme
Proceedings of the 2001 international symposium on Physical design
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test
Journal of Electronic Testing: Theory and Applications
Comparative Cost Analysis for Smart-Substrate MCM Systems
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
5.2 Self-Timed Boundary-Scan Cells for Multi-Chip Module Test
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
2.5D system integration: a design driven system implementation schema
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
2.5-Dimensional VLSI system integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This implementation strategy enables incremental test of all system components, providing an alternative solution to the known good die testing problem. The authors present a simple microcontroller emulator designed and fabricated for study of the test logic needed as a key component of this method.