Self-Timed Boundary-Scan Cells for Multi-Chip Module Test

  • Authors:

  • T. A. García;A. J. Acosta;J. M. Mora;J. Ramos;J. L. Huertas

  • Affiliations:

  • Instituto de Microelectrónica de Sevilla, CNM-Universidad de Sevilla, Edificio CICA, Avda de Reina Mercedes s/n, 41012—Sevilla, Spain;Instituto de Microelectrónica de Sevilla, CNM-Universidad de Sevilla, Edificio CICA, Avda de Reina Mercedes s/n, 41012—Sevilla, Spain. acojim@imse.cnm.es;Instituto de Microelectrónica de Sevilla, CNM-Universidad de Sevilla, Edificio CICA, Avda de Reina Mercedes s/n, 41012—Sevilla, Spain;Instituto de Microelectrónica de Sevilla, CNM-Universidad de Sevilla, Edificio CICA, Avda de Reina Mercedes s/n, 41012—Sevilla, Spain;Instituto de Microelectrónica de Sevilla, CNM-Universidad de Sevilla, Edificio CICA, Avda de Reina Mercedes s/n, 41012—Sevilla, Spain

  • Venue:
  • Journal of Electronic Testing: Theory and Applications
  • Year:
  • 1999

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Abstract

This paper presents a self-timed scan-path architecture, tobe used in a conventional synchronous environment, and with basicapplication in digital testing and interconnections checking in aSmart-Substrate MCM (T.A. García, A.J. Acosta, J.M. Mora, J.Ramos, and J.L. Huertas, “Self-Timed Boundary-Scan Cells forMulti-Chip Module Test,” Proceedings of IEEE VLSI TestSymposium, April 1998, pp. 92–97). With this approach, thepotential advantages of self-timed asynchronous systems are exploredfor their practical use in a classical MCM testing application.Three different self-timed asynchronous boundary scan cells areproposed (Sense, Drive and Drive & Sense cells) that can be connectedto form a self-timed scan-path. The main advantage is that no globaltest clock is needed, avoiding clock skew and synchronization faultsin test mode, and hence, a more reliable test process is achieved.These cells have been designed and integrated in active substrates,building several boundary-scan configurations and being fullycompatible with the ANSI/IEEE 1149.1 Standard. The experimentalresults, as well as their comparison with their synchronouscounterparts, show the feasibility of the proposed self-timedapproach for testing interconnections in a MCM.