Self-Timed Boundary-Scan Cells for Multi-Chip Module Test
Journal of Electronic Testing: Theory and Applications
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
DSP architectures: past, present and futures
ACM SIGARCH Computer Architecture News
Simulation of gate circuits in the algebra of transients
CIAA'02 Proceedings of the 7th international conference on Implementation and application of automata
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We have designed asynchronous standby circuits for a pager decoder which dissipate four times less power and are 40\% larger in size than synchronous designs. For the total pager unit this means a 37\% reduction in power dissipation for nearly no additional area. The decoder chip, which apart from the standby circuits is completely synchronous, has been fabricated and was first-time-right. Two problems had to be solved to incorporate asynchronous subcircuits in a synchronous environment: synchronization and testing. A synchronization scheme is described that allows a free intermixing of asynchronous and synchronous modules and a test strategy is proposed in which the scan test facilities in the synchronous environment are used to test the asynchronous modules. One function is prevalent in the standby circuits, namely counting. In the appendix we present the asynchronous design of a so-called loadable counter whose power consumption does not depend on its size.