Prospects for WSI: A Manufacturing Perspective
Computer - Special issue on wafer-scale integration
Smart-Substrate Multichip-Module Systems
IEEE Design & Test
A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Feasibility Study of Smart Substrate Multichip Modules
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Fundamentals of MCM Testing and Design-for-Testability
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test
Journal of Electronic Testing: Theory and Applications
5.2 Self-Timed Boundary-Scan Cells for Multi-Chip Module Test
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
2.5D system integration: a design driven system implementation schema
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
2.5-Dimensional VLSI system integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a cost-based assessment of the effectiveness of Smart Substrate MCM Systems. A Smart Substrate MCM System is one in which the substrate contains active circuitry for carrying out testing functions. The feasibility of using this approach is investigated. The Smart Substrate strategy is compared to an alternative approach based on the assumption that system components are perfect (“Known Good Die (KGD)” approach). The obtained results identify the domain of applicability of Smart substrate MCMs and point to limitations of the KGD approach.