5.2 Self-Timed Boundary-Scan Cells for Multi-Chip Module Test

Authors:
T. A. García;J. L. Huertas
Affiliations:
-;-
Venue:
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Year:
1998

Citing 5
Cited 1

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Abstract

This communication presents a self-timed scan-path architecture, to be used in a conventional synchronous environment, and with basic application in digital testing in a Smart-Substrate MCM. Three different self-timed asynchronous scan cells are proposed (Sense, Drive and Drive&Sense cells) that can be connected to form a self-timed scan-path. The main advantage is that no global test clock is needed, avoiding clock skew and synchronization faults in test mode.