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IEEE Design & Test
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IEEE Design & Test
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Proceedings of the IEEE International Test Conference 2001
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Proceedings of the IEEE International Test Conference
Test and repair of large embedded DRAMs. I
Proceedings of the IEEE International Test Conference 2001
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Physical Design of the "2.5D" Stacked System
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Proceedings of the Conference on Design, Automation and Test in Europe
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The excessive interconnection delay and fast increasing development cost, as well as complexity of the single-chip integration of different technologies, are likely to become the major stumbling blocks for the success of monolithic system-on-chips. To address the above problems, this paper investigates a new VLSI integration paradigm, the so-called 2.5-dimensional (2.5-D) integration scheme. Using this scheme, a VLSI system is implemented as a three-dimensional stacking of monolithic chips. A cost analysis framework was developed to justify the 2.5-D integration scheme from an economic point of view. Enabling technologies for the new integration scheme are also reviewed.