Introducing Core-Based System Design
IEEE Design & Test
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST
Proceedings of the IEEE International Test Conference
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A General Purpose IDDQ Measurement Circuit
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Towards design and validation of mixed-technology SOCs
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
MetaCores: design and optimization techniques
Proceedings of the 38th annual Design Automation Conference
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On Concurrent Test of Core-Based SOC Design
Journal of Electronic Testing: Theory and Applications
The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs
Journal of Electronic Testing: Theory and Applications
On-Chip Clock Faults' Detector
Journal of Electronic Testing: Theory and Applications
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM
Journal of Electronic Testing: Theory and Applications
Using a Soft Core in a SoC Design: Experiences with picoJava
IEEE Design & Test
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test and Debug Strategy of the PNX8525 Nexperia" Digital Video Platform System Chip
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test Features of a Core-Based Co-Processor Array for Video Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Hierarchical Infrastructure for SoC Test Management
IEEE Design & Test
The Universal Configurable Block/Machine—An Approach for a Configurable SoC-Architecture
The Journal of Supercomputing
IEEE Transactions on Computers
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 2
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
2.5D system integration: a design driven system implementation schema
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Technique for High Ratio LZW Compression
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores
IEEE Transactions on Computers
A new design-for-test technique for reducing SOC test time
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Test infrastructure design for mixed-signal SOCs with wrapped analog cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test environment for embedded cores-based system-on-chip (soc): development and methodologies
MIC'06 Proceedings of the 25th IASTED international conference on Modeling, indentification, and control
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
IEEE Design & Test
Power-aware SoC test planning for effective utilization of port-scalable testers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power multi-core ATPG to target concurrency
Integration, the VLSI Journal
Wafer-level modular testing of core-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MTNet: design of a wireless test framework for heterogeneous nanometer systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE standard 1500 compliance verification for embedded cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test-length and TAM optimization for wafer-level reduced pin-count testing of core-based SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-Area Wrapper Cell Design for Hierarchical SoC Testing
Journal of Electronic Testing: Theory and Applications
IEEE standard 1500 compatible delay test framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock tree synthesis with pre-bond testability for 3D stacked IC designs
Proceedings of the 47th Design Automation Conference
Test-access mechanism optimization for core-based three-dimensional SOCs
Microelectronics Journal
On-chip SOC test platform design biased on IEEE 1500 standard
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2.5-Dimensional VLSI system integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 4.11 |
Recently, designers have been embedding reusable modules to build on-chip systems that form rich libraries of predesigned, preverified building blocks. These embedded cores make it easier to import technology to a new system and differentiate the corresponding product by leveraging intellectual property advantages. Most importantly, design reuse shortens the time-to-market for new systems.The attributes that make system chips built with embedded IP cores an attractive methodology--design reuse, heterogeneity, reconfigurability, and customizability--also make testing and debugging these chips a complex challenge.The authors review the various alternatives for testing embedded cores and describe solutions and proposed standards that are expected to play a key role in developing the core-based design paradigm.