The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
microSPARCTM: A Case Study of Scan-Based Debug
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Macro Testability: The Results of Production Device Applications
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
The Role of Test Protocols in Testing Embedded-Core-Based System ICs
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Silicon debug of a co-processor array for video applications
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
What defects escape our tests ... and how will we detect them in the future ?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Features of a Core-Based Co-Processor Array for Video Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Silicon Debug: Scan Chains Alone Are Not Enough
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Macro Testing: Unifying IC And Board Test
IEEE Design & Test
Challenges in testing core-based system ICs
IEEE Communications Magazine
Wrapper design for multifrequency IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Post-silicon platform for the functional diagnosis and debug of networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Decreasing feature sizes and increasing customerdemand for more functionality have forced designteams to re-use design blocks and applicationplatforms. As a result, re-use of test, design-for-testand design-for-debug for large system chips isbecoming increasingly important and increasinglynecessary. In this paper, the test and debug featuresof the Nexperia驴 PNX8525 chip are presented. ThePNX8525 chip is a large system chip for theconsumer electronics market. The impact of core-basedtesting is discussed, at both the core-level andthe top-level, together with the design-for-debugimplementation on this multiple clock domain chip.