System chip test: how will it impact your design?
Proceedings of the 37th Annual Design Automation Conference
Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Electronic Testing: Theory and Applications
The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs
Journal of Electronic Testing: Theory and Applications
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
Journal of Electronic Testing: Theory and Applications
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
CTL the Language for Describing Core-Based Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test and Debug Strategy of the PNX8525 Nexperia" Digital Video Platform System Chip
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test Features of a Core-Based Co-Processor Array for Video Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An novel methodology for reducing SoC test data volume on FPGA-based testers
Proceedings of the conference on Design, automation and test in Europe
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A core-based design style introduces new test challenges, which, if not dealt with properly, might defeat the entire purpose of using pre-designed cores. Macro Test is a liberal test approach for core-based designs, i.e., it supports all kinds of test access mechanisms to the embedded cores. The separation of tests into test protocols and test patterns plays a crucial role in Macro Test. Tasks as expansion of core-level tests to chip level, scheduling of tests, and test assembly are carried out on test protocols by software tools. This paper addresses the role of test protocols and features an example of a small scan-testable core. We argue that the fact that expansion and scheduling take place on test protocols rather than on complete tests is important to reduce the computational complexity of the associated software tools.