A fast and low cost testing technique for core-based system-on-chip
DAC '98 Proceedings of the 35th annual Design Automation Conference
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
System chip test: how will it impact your design?
Proceedings of the 37th Annual Design Automation Conference
Test scheduling for core-based systems
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An integrated system-on-chip test framework
Proceedings of the conference on Design, automation and test in Europe
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
Introducing Core-Based System Design
IEEE Design & Test
An Industrial Approach to Core-Based System Chip Testing
VLSI-SOC '01 Proceedings of the IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip: SOC Design Methodologies
Macro Testability: The Results of Production Device Applications
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
Proceedings of the IEEE International Test Conference
A novel test methodology for core-based system LSIs and a testing time minimization problem
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip
Proceedings of the IEEE International Test Conference 2001
CTL the language for describing core-based test
Proceedings of the IEEE International Test Conference 2001
The Role of Test Protocols in Testing Embedded-Core-Based System ICs
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Conversion of Small Functional Test Sets of Nonscan Blocks to Scan Patterns
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Cluster-Based Test Architecture Design for System-on-Chip
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Features of a Core-Based Co-Processor Array for Video Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Challenges in testing core-based system ICs
IEEE Communications Magazine
Test scheduling for core-based systems using mixed-integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 39th annual Design Automation Conference
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computers
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Modular testing is an attractive approach to testing large system ICs, especially if they are built from pre-designed reusable embedded cores. This paper describes an automated modular test development approach. The basis of this approach is that a core or module test is dissected into a test protocol and a test pattern list. A test protocol describes in detail how to apply one test pattern to the core, while abstracting from the specific test pattern stimulus and response values. Subsequent automation tasks, such as the expansion from core-level tests to system-chip-level tests and test scheduling, all work on test protocols, thereby greatly reducing the amount of compute time and data involved. Finally, an SOC-level test is assembled from the expanded and scheduled test protocols and the (so far untouched) test patterns. This paper describes and formalizes the notion of test protocols and the algorithms for test protocol expansion and scheduling. A running example is featured throughout the paper. We also elaborate on the industrial usage of the concepts described.