Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Minimizing concurrent test time in SoC's by balancing resource usage
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
The design and optimization of SOC test solutions
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On IEEE P1500's Standard for Embedded Core Test
Journal of Electronic Testing: Theory and Applications
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Journal of Electronic Testing: Theory and Applications
On Concurrent Test of Core-Based SOC Design
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
On Test Scheduling for Core-Based SOCs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Constraint Driven Pin Mapping for Concurrent SOC Testing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Optimization of Test Accesses with a Combined BIST and External Test Scheme
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Design of reconfigurable access wrappers for embedded core based SoC test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
A Graph-Based Approach to Power-Constrained SOC Test Scheduling
Journal of Electronic Testing: Theory and Applications
SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
A Note on System-on-Chip Test Scheduling Formulation
Journal of Electronic Testing: Theory and Applications
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level
Journal of Electronic Testing: Theory and Applications
FITS: An Integrated ILP-Based Test Scheduling Environment
IEEE Transactions on Computers
A new design-for-test technique for reducing SOC test time
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
SoC test scheduling using the B-tree based floorplanning technique
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
STEAC: a platform for automatic SOC test integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
WSEAS Transactions on Circuits and Systems
Test time minimization for hybrid BIST of core-based systems
Journal of Computer Science and Technology
Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach
ICIC '07 Proceedings of the 3rd International Conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm
Computers and Electrical Engineering
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We present optimal solutions to the test scheduling problem for core-based systems. Given a set of tasks (test sets for the cores), a set of test resources (e.g., test buses, BIST hardware) and a test access architecture, we determine start times for the tasks such that the total test application time is minimized. We show that the test scheduling decision problem is equivalent to the m-processor open shop scheduling problem and is therefore NP-complete. However a commonly encountered instance of this problem (m=2) can be solved in polynomial time. For the general case (m>2), we present a mixed-integer linear programming (MILP) model for optimal scheduling and apply it to a representative core-based system using an MILP solver available in the public domain. We also extend the MILP model to allow optimal test set selection from a set of alternatives. Finally, we present an efficient heuristic algorithm for handling larger systems for which the MILP model may be infeasible