Evolutionary computation: toward a new philosophy of machine intelligence
Evolutionary computation: toward a new philosophy of machine intelligence
Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
FAST-SP: a fast algorithm for block placement based on sequence pair
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
SOC Test Scheduling Using Simulated Annealing
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On the Use of k-tuples for SoC Test Schedule Representation
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test scheduling for core-based systems using mixed-integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A retention-aware test power model for embedded SRAM
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
SoC test scheduling using the B-tree based floorplanning technique
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Power-constrained test scheduling for multi-clock domain SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers
Proceedings of the conference on Design, automation and test in Europe
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
WSEAS Transactions on Circuits and Systems
Scheduling Power-Constrained Tests through the SoC Functional Bus
IEICE - Transactions on Information and Systems
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint
IEICE - Transactions on Information and Systems
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
IEICE - Transactions on Information and Systems
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
IEICE - Transactions on Information and Systems
Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach
ICIC '07 Proceedings of the 3rd International Conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence
Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm
Computers and Electrical Engineering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a new algorithm to co-optimize test scheduling andwrapper design under power constraints for core-based SoCs(System on Chip). Core testing solutions are generated as a set ofwrapper designs, each represented by a rectangle with width equalto the test time and height equal to the number of TAM (TestAccess Mechanism) wires used. The test-scheduling problem withpower constraints is formulated as the distributed rectangle bin-packingproblem, which allows wrapper pins to be assigned to non-consecutiveSoC pins. The generalized problem for multiple-TAMsis solved by global optimization using evolutionary strategy and thesequence-pair representation. Experiments on ITCý02 benchmarksare very encouraging.