A fast and low cost testing technique for core-based system-on-chip
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
An integrated system-on-chip test framework
Proceedings of the conference on Design, automation and test in Europe
Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Using Partial Isolation Rings to Test Core-Based Designs
IEEE Design & Test
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Testing Reusable IP - A Case Study
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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Test access mechanisms (TAMs) and test wrappers are integralparts of a system-on-chip (SOC) test architecture. Prior researchhas concentrated on only one aspect of the TAM/wrapper designproblem at a time, i.e., either optimizing the TAMs for a set ofpre-designed wrappers, or optimizing the wrapper for a given TAMwidth. In this paper, we address a more general problem, that ofcarrying out TAM design and wrapper optimization in conjunction.We present an efficient algorithm to construct wrappers that reducethe testing time for cores. Our wrapper design algorithm improveson earlier approaches by also reducing the TAM width required toachieve these lower testing times. We present new mathematicalmodels for TAM optimization that use the core testing time valuescalculated by our wrapper design algorithm. We further present anew enumerative method for TAM optimization that reduces executiontime significantly when the number of TAMs being designed issmall. Experimental results are presented for an academic SOC aswell as an industrial SOC.