A fast and low cost testing technique for core-based system-on-chip

Authors:
Indradeep Ghosh;Sujit Dey;Niraj K. Jha
Affiliations:
Department of Electrical Engineering, Princeton University, Princeton, NJ;Department of Electrical & Computer Engineering, University of California, San Diego, La Jolla, CA;Department of Electrical Engineering, Princeton University, Princeton, NJ
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

Citing 10
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Abstract

This paper proposes a new methodology for testing a core-based system-on-chip (SOC), targeting the simultaneous reduction of test area overhead and test application time. Testing of embedded cores is achieved using the transparency properties of surrounding cores. At the core level, testability and transparency can be achieved by reusing existing logic inside the core, and providing different versions of the core having different area overheads and transparency latencies. At the chip level, the technique analyzes the topology of the SOC to select the core versions that best meet the user's desired test area overhead and test application time objectives. Application of the method to example SOCs demonstrates the ability to design highly testable SOCs with minimized test area overhead, minimized test application time, or a desired trade-off between the two. Significant reduction in area overhead and test application time compared to an existing SOC testing technique is also demonstrated.